Analog Multiplexer Single 8:1/Dual 4:1 28-Pin PDIP, DG538ADJ-E3, Vishay

The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing.The DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a “T” configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to -97 dB at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up.

  • Wide Bandwidth: 500 MHz
  • Very Low Crosstalk: –97 dB @ 5 MHz
  • On-Board TTL-Compatible Latches with Readback
  • Optional Negative Supply
  • Low RDS(on): 45
  • Single-Ended or Differential Operation
  • Latch-up Proof

Характеристики

Бренд

Chip_enable_signals

Yes

Max_on_resistance

90@15V@-3V Ohm

Number_of_channels_per_chip

1, 2

Number_of_outputs_per_chip

2

Max_turn_on_time

300@15V@-3V ns

Output_signal_type

Single

Power_supply_type

Dual, Single

Max_propagation_delay_btb

300@15V/300@-3V ns

Max_on_resist_range

80 to 100 Ohm

Number_of_inputs_per_chip

8

Max_high_lev_output_current

40 mA

Msl_level

1

Конфигурация

Dual 4:1, Single 8:1

Eccn

EAR99

Htsn

8542390001

Input_signal_type

Single

Kind

Analog Multiplexer

Lead_finish

Matte Tin

Max_power_dissipation

625 mW

Max_processing_temp

260

Mounting

Through Hole

Operat_supply_current

2@15V

Operat_supply_voltage

±10, ±12 V, ±15, 10, 18

Operat_temperature

-40 to 85 °C

Pin_count

28

Product_dimensions

39.7 x 14.73 x 3.31 mm

Schedule_b

8542390000

Specifications

http://www.vishay.com/docs/70069/70069.pdf

Supplier_package

PDIP

Артикул: DG538ADJ-E3

Описание

The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing.The DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a “T” configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to -97 dB at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up.

  • Wide Bandwidth: 500 MHz
  • Very Low Crosstalk: –97 dB @ 5 MHz
  • On-Board TTL-Compatible Latches with Readback
  • Optional Negative Supply
  • Low RDS(on): 45
  • Single-Ended or Differential Operation
  • Latch-up Proof

Детали

Бренд

Chip_enable_signals

Yes

Max_on_resistance

90@15V@-3V Ohm

Number_of_channels_per_chip

1, 2

Number_of_outputs_per_chip

2

Max_turn_on_time

300@15V@-3V ns

Output_signal_type

Single

Power_supply_type

Dual, Single

Max_propagation_delay_btb

300@15V/300@-3V ns

Max_on_resist_range

80 to 100 Ohm

Number_of_inputs_per_chip

8

Max_high_lev_output_current

40 mA

Msl_level

1

Конфигурация

Dual 4:1, Single 8:1

Eccn

EAR99

Htsn

8542390001

Input_signal_type

Single

Kind

Analog Multiplexer

Lead_finish

Matte Tin

Max_power_dissipation

625 mW

Max_processing_temp

260

Mounting

Through Hole

Operat_supply_current

2@15V

Operat_supply_voltage

±10, ±12 V, ±15, 10, 18

Operat_temperature

-40 to 85 °C

Pin_count

28

Product_dimensions

39.7 x 14.73 x 3.31 mm

Schedule_b

8542390000

Specifications

http://www.vishay.com/docs/70069/70069.pdf

Supplier_package

PDIP