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ADC Dual Pipelined 250Msps 14-bit Parallel/Serial/LVDS 64-Pin VQFN EP T/R, ADS4249IRGCT, Texas Instruments

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package

    • Характеристики

    Volt_supply_source

    Single
    Number_of_analog_inputs

    2
    Sampling_rate

    250 Msps
    Volt_reference

    Internal
    Digital_supply_support

    No
    Architecture

    Pipelined
    Resolution

    14 Bit
    Differential_nonlinearity

    -0.95, 1.7 LSB
    Signal_to_noise_ratio

    72.8 dBFS
    Input_type

    Voltage
    Input_signal_type

    Differential
    Input_volt

    2 Vp-p
    Бренд

    Msl_level

    3
    Country_of_origin

    Thailand
    Eccn

    3A991.C.3
    Htsn

    8542390001
    Lead_finish

    Gold
    Max_processing_temp

    260
    Mounting

    Surface Mount
    Operating_temp

    -40 to 85 °C
    Pin_count

    64
    Product_dimensions

    9 x 9 x 0.88 mm
    Schedule_b

    8542390000
    Screening_level

    Industrial
    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS4249&&fileType=pdf
    Supplier_package

    VQFN EP
    Operating_supply_volt

    1.7, 1.8 V, 1.9
    Number_of_adcs

    2
    Digital_interface_type

    LVDS, Parallel, Serial
    SKU: ADS4249IRGCT

    Description

    The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package

    • Additional information

    Volt_supply_source

    Single
    Number_of_analog_inputs

    2
    Sampling_rate

    250 Msps
    Volt_reference

    Internal
    Digital_supply_support

    No
    Architecture

    Pipelined
    Resolution

    14 Bit
    Differential_nonlinearity

    -0.95, 1.7 LSB
    Signal_to_noise_ratio

    72.8 dBFS
    Input_type

    Voltage
    Input_signal_type

    Differential
    Input_volt

    2 Vp-p
    Бренд

    Msl_level

    3
    Country_of_origin

    Thailand
    Eccn

    3A991.C.3
    Htsn

    8542390001
    Lead_finish

    Gold
    Max_processing_temp

    260
    Mounting

    Surface Mount
    Operating_temp

    -40 to 85 °C
    Pin_count

    64
    Product_dimensions

    9 x 9 x 0.88 mm
    Schedule_b

    8542390000
    Screening_level

    Industrial
    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS4249&&fileType=pdf
    Supplier_package

    VQFN EP
    Operating_supply_volt

    1.7, 1.8 V, 1.9
    Number_of_adcs

    2
    Digital_interface_type

    LVDS, Parallel, Serial

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