ADC Single Pipelined 80Msps 12-bit Parallel/Serial/LVDS 32-Pin VQFN EP T/R, ADS61B23IRHBT, Texas Instruments

ADS61B23 is a12-bit A/D converter (ADC) with a maximum sampling frequency of80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.ADS61B23 has coarse and finegain options that are used to improve SFDR performance at lower full-scale analog input ranges.The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up. ADS61B23 includesinternal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. 

  • Maximum Sample Rate: 80 MSPS
  • 12-bit Resolution with No Missing Codes
  • Buffered Analog Inputs with
    • Very Low Input Capacitance (< 2 pF)
    • High DC Resistance (5 kO)
  • 82 dBc SFDR and 70 dBFS SNR
    (-1 BFS or 1.8 Vpp input)
  • 85 dBc SFDR (-6 dBFS or 1 Vpp input)
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • External Decoupling Eliminated for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-pin QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • Temperature range -40°C to 85°C
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
  • Характеристики

    Volt_supply_source

    Single

    Number_of_analog_inputs

    1

    Sampling_rate

    80 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    No

    Architecture

    Pipelined

    Resolution

    12 Bit

    Typical_power_dissipation

    351 mW

    Differential_nonlinearity

    -0.75, 2 LSB

    Signal_to_noise_ratio

    70.2 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    2 Vp-p

    Бренд

    Msl_level

    3

    Country_of_origin

    United States

    Eccn

    EAR99

    Htsn

    8542390001

    Lead_finish

    Gold

    Max_power_dissipation

    475 mW

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    32

    Product_dimensions

    5 x 5 x 0.9 mm

    Schedule_b

    8542390000

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS61B23&&fileType=pdf

    Supplier_package

    VQFN EP

    Operating_supply_volt

    3, 3.3 V, 3.6

    Number_of_adcs

    1

    Digital_interface_type

    LVDS, Parallel, Serial

    SKU: ADS61B23IRHBT

    Description

    ADS61B23 is a12-bit A/D converter (ADC) with a maximum sampling frequency of80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.ADS61B23 has coarse and finegain options that are used to improve SFDR performance at lower full-scale analog input ranges.The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up. ADS61B23 includesinternal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. 

  • Maximum Sample Rate: 80 MSPS
  • 12-bit Resolution with No Missing Codes
  • Buffered Analog Inputs with
    • Very Low Input Capacitance (< 2 pF)
    • High DC Resistance (5 kO)
  • 82 dBc SFDR and 70 dBFS SNR
    (-1 BFS or 1.8 Vpp input)
  • 85 dBc SFDR (-6 dBFS or 1 Vpp input)
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • External Decoupling Eliminated for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-pin QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • Temperature range -40°C to 85°C
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
  • Additional information

    Volt_supply_source

    Single

    Number_of_analog_inputs

    1

    Sampling_rate

    80 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    No

    Architecture

    Pipelined

    Resolution

    12 Bit

    Typical_power_dissipation

    351 mW

    Differential_nonlinearity

    -0.75, 2 LSB

    Signal_to_noise_ratio

    70.2 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    2 Vp-p

    Бренд

    Msl_level

    3

    Country_of_origin

    United States

    Eccn

    EAR99

    Htsn

    8542390001

    Lead_finish

    Gold

    Max_power_dissipation

    475 mW

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    32

    Product_dimensions

    5 x 5 x 0.9 mm

    Schedule_b

    8542390000

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS61B23&&fileType=pdf

    Supplier_package

    VQFN EP

    Operating_supply_volt

    3, 3.3 V, 3.6

    Number_of_adcs

    1

    Digital_interface_type

    LVDS, Parallel, Serial