MCU 32-bit SuperH RISC 256KB Flash 5V 80-Pin PQFP, HD64F7046F50V, Renesas Electronics

The SH7046 Group single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration.The SH7046 Group CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds.In addition, the SH7046 Group includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports.There are two versions of on-chip ROM: F-ZTAT (Flexible Zero Turn Around Time) that includes flash memory, and mask ROM. The flash memory can be programmed with a programmer that supports SH7046 Group programming, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board.

  • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
    • Instruction length: 16-bit fixed length for improved code efficiency
    • Load-store architecture (basic operations are executed between registers)
    • Sixteen 32-bit general registers
    • Five-stage pipeline
    • On-chip multiplier: multiplication operations (32 bits × 32 bits ? 64 bits) executed in two to four cycles
    • C language-oriented 62 basic instructions
  • Various peripheral functions
    • Data transfer controller (DTC)
    • Multifunction timer/pulse unit (MTU)
    • Motor management timer(MMT)
    • Compare match timer (CMT)
    • Watchdog timer (WDT)
    • Asynchronous or clocked synchronous serial communication interface(SCI)
    • 10-bit A/D converter
    • Clock pulse generator
    • User break controller (UBC)

Характеристики

Number_of_programmable_i_os

42

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/RNSA/RNSAS01266/RNSAS01266-1.pdf?hkey=52A5661711E402568146F3353EA87419

On_chip_adc

12-chx10-bit

Operating_supply_voltage

5 V

Operating_temperature

-20 to 75 °C

Pin_count

80

Product_dimensions

14 x 14 x 2.7 mm

Program_memory_type

Flash

Mounting

Surface Mount

Schedule_b

8542310000

Number_of_timers

7

Msl_level

3

Supplier_package

PQFP

Бренд

Data_bus_width

32 Bit

Eccn

3A991

Htsn

8542310001

Max_speed

50 MHz

Instruction_set_architecture

RISC

Тип интерфейса

SCI

Lead_finish

Gold, Tin/Bismuth, Tin/Copper

Max_processing_temp

260 °C

SKU: HD64F7046F50V

Description

The SH7046 Group single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration.The SH7046 Group CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds.In addition, the SH7046 Group includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports.There are two versions of on-chip ROM: F-ZTAT (Flexible Zero Turn Around Time) that includes flash memory, and mask ROM. The flash memory can be programmed with a programmer that supports SH7046 Group programming, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board.

  • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
    • Instruction length: 16-bit fixed length for improved code efficiency
    • Load-store architecture (basic operations are executed between registers)
    • Sixteen 32-bit general registers
    • Five-stage pipeline
    • On-chip multiplier: multiplication operations (32 bits × 32 bits ? 64 bits) executed in two to four cycles
    • C language-oriented 62 basic instructions
  • Various peripheral functions
    • Data transfer controller (DTC)
    • Multifunction timer/pulse unit (MTU)
    • Motor management timer(MMT)
    • Compare match timer (CMT)
    • Watchdog timer (WDT)
    • Asynchronous or clocked synchronous serial communication interface(SCI)
    • 10-bit A/D converter
    • Clock pulse generator
    • User break controller (UBC)

Additional information

Number_of_programmable_i_os

42

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/RNSA/RNSAS01266/RNSAS01266-1.pdf?hkey=52A5661711E402568146F3353EA87419

On_chip_adc

12-chx10-bit

Operating_supply_voltage

5 V

Operating_temperature

-20 to 75 °C

Pin_count

80

Product_dimensions

14 x 14 x 2.7 mm

Program_memory_type

Flash

Mounting

Surface Mount

Schedule_b

8542310000

Number_of_timers

7

Msl_level

3

Supplier_package

PQFP

Бренд

Data_bus_width

32 Bit

Eccn

3A991

Htsn

8542310001

Max_speed

50 MHz

Instruction_set_architecture

RISC

Тип интерфейса

SCI

Lead_finish

Gold, Tin/Bismuth, Tin/Copper

Max_processing_temp

260 °C