Description
The SH7708, SH7708S, and SH7708R(SH7708 Series) are 32-bit RISC (reduced instruction set computer) microcomputers, featuring object code upward-Compatibility with SH-1 and SH-2 microcomputers. The SH7708R is completely pin compatible with the SH7708S. It includes an 8-kbyte cache with a choice of write-back or write-through mode, and an MMU (memory management unit) with a 128-entry 4-way set associative TLB (translation look aside buffer).The SH7708 Series have an on-chip bus state controller (BSC) that allows direct connection to DRAM, synchronous DRAM (SDRAM), and pseudo-SRAM (PSRAM) without external circuitry. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
- Original Hitachi SuperH RISC engine architecture
- 32-bit internal data bus
- General-register machine
- Sixteen 32-bit general registers (eight 32-bit bank registers)
- Five 32-bit control registers
- Four 32-bit system registers
- RISC-type instruction set (upward compatibility with the SH-1 and SH-2 series)
- Instruction length: 16-bit fixed length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- C-oriented instruction set
- Instruction execution time: one instruction/cycle for basic instructions
- Logical address space: 4 Gbytes (448-Mbyte actual memory space)
- Space identifier ASID: 8 bits, 256 logical address spaces
- On-chip multiplier
- Five-stage pipeline
- Clock mode: selected from an on-chip oscillator module, a frequency doubling circuit, or a clock output by combining them by PLL synchronization
- Processing states:
- Power-on reset state
- Manual reset state
- Exception processing state
- Program execution state
- Power-down state
- Bus-released state
- Power-down modes:
- Sleep mode
- Standby mode
- Hardware Standby mode
- On-chip clock pulse generator
- One watchdog timer channel
