Description
The SH7604 is a new-generation single-chip RISC microprocessor that integrates a Hitachioriginal CPU, a multiplier, cache memory, and peripheral functions required for system configuration.The CPU features a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the on-chip 4-kbyte cache memory and divider enhance data processing ability.The SH7604 is also provided with on-chip peripheral functions including a direct memory access controller (DMAC), timers, a serial communication interface (SCI), and an interrupt controller. External memory access support functions (provided by the bus state controller) enable direct connection to DRAM, synchronous DRAM, and pseudo-SRAM.The high-speed CPU and comprehensive peripheral functions enable designers to construct highperformance systems with advanced functionality at low cost, even in applications such as realtime control that require very high speeds, impossible with conventional microprocessors.
- CPU:
- Original Hitachi architecture
- 32bit internal configuration
- General-registers:
- Sixteen 32bit general registers
- Three 32bit control registers
- Four 32bit system registers
- RISC-type instruction set:
- Instruction length: 16bit fixed length for improved code efficiency
- Load-store architecture
- Delayed conditional/unconditional branch instructions reduce pipeline disruption during branching
- Instruction set based on C language
- Instruction execution time: one instruction/state
- Address space: 4Gbytes available in the architecture
- On-chip multiplier: multiply operations (32bits – 32bits x 64bits) and multiply-and accumulate operations (32bits x 32bits + 64 bits – 64 bits) executed in 2 to 4 states
- Five-stage pipeline
- Operating Modes:
- Clock mode: selected from the combination of an on-chip oscillator module, a frequency multiplier, clock output, PLL synchronization, and 90° phase shifting (the range of choices depends on the package)
- Slave/master mode
- Processing states
- Power-on reset state
- Manual reset state
- Exception handling state
- Program execution state
- Power-down state
- Bus-released state
- Power-down states
- Sleep mode
- Standby mode
- Module stop mode
- Interrupt Controller:
- Five external interrupt pins (NMI, IRL0 to IRL3), encoded input of 15 external interrupt sources via pins IRL0 to IRL3
- Twelve internal interrupt sources (DMAC x 2, DIVU x 1, FRT x 3, WDT x 1, SCI x— 4, REF x 1)
- Sixteen programmable priority levels
- Vector number settable for each internal interrupt source
- Auto-vector or external vector selectable as vector for external interrupts via pins IRL0 to IRL3
- User Break Controller (UBC):
- Generates an interrupt when the CPU or DMAC generates an address, data, or bus cycle with the specified conditions (address, data, CPU cycle/non-CUP cycle, instruction fetch/data access, read/write, byte/word/longword access)
- Simplifies configuration of a self-debugger
- Clock Pulse Generator (CPG)/Phase Locked Loop (PLL):
- On-chip clock pulse generator
- Crystal clock source or external clock source can be selected
- Clock multiplication (x1, x2, x4), PLL synchronization, or 90° phase shift can be selected
- Supports clock pause function for frequency change of external clock
- Bus State Controller:
- Supports external memory access
- 32bit external data bus
- Memory address space divided into four areas. It is possible to set the following characteristics for each area(32Mbyte linear):
- Bus size (8,16,or32bits)
- Number of wait cycles settable or not settable
- Setting the memory space type simplifies connection to DRAM, synchronous DRAM, pseudo-SRAM, and burst ROM
- Outputs signals RAS, CAS, CE, and OE corresponding to DRAM, synchronous DRAM, and pseudo-SRAM areas
- Tp cycles can be generated to assure RAS precharge time
- Address multiplexing is supported internally, so DRAM and synchronous DRAM can be connected directly
- Outputs chip select signals (CS0 to CS3) for each area
- DRAM/synchronous DRAM/pseudo-SRAM refresh functions
- Programmable refresh interval
- Supports CAS-before-RAS refresh and self-refresh modes
- DRAM/synchronous DRAM/pseudo-SRAM burst access function
- Supports high-speed access modes for DRAM/synchronous DRAM/pseudo-SRAM
- Wait cycles can be inserted by an external WAIT signal
