Description
This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1,SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750 and SH7750S have an 8-Kbyte instruction cache and a 16-Kbyte data cache. The SH7750R has a 16-Kbyte instruction cache and a 32-Kbyte data cache.This LSI has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
- Superscalar architecture: Parallel execution of two instructions
- External buses
- Separate 26-bit address and 64-bit data buses
- External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency
- Renesas original SuperH architecture
- 32-bit internal data bus
- General register file:
- Sixteen 32-bit general registers (and eight 32-bit shadow registers)
- Seven 32-bit control registers
- Four 32-bit system registers
- RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3)
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- Conditional execution
- C-based instruction set
- Superscalar architecture (providing simultaneous execution of two instructions) including FPU
- Instruction execution time: Maximum 2 instructions/cycle
- Virtual address space: 4 Gbytes (448-Mbyte external memory space)
- Space identifier ASIDs: 8 bits, 256 virtual address spaces
- On-chip multiplier
- Five-stage pipeline
