Описание
Microchip"s PIC32MZ1024ECG064 32-bit Microcontrollers provide class-leading performance of 330 DMIPS and 3.28 CoreMarks/MHz, along with dual-panel, live-update Flash (up to 2MB), large RAM (512KB) and the connectivity peripherals—including a 10/100 Ethernet MAC, Hi-Speed USB MAC/PHY (a first for PIC MCUs) and dual CAN ports—needed to support today"s demanding applications. The PIC32MZ also has class-leading code density that is 30% better than competitors, along with a 28Msps ADC that offers one of the best throughput rates for 32-bit MCUs. Rounding out this family"s high level of integration is a full-featured hardware crypto engine with a random number generator for high-throughput data encryption/decryption and authentication (e.g., AES, 3DES, SHA, MD5 and HMAC), as well as the first SQI interface on a Microchip MCU and the PIC32"s highest number of serial channels. The MIPS32 microAptiv Microprocessor Core is the heart of the PIC32MZ EC family device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. The MIPS32 microAptiv Microprocessor core in PIC32MZ EC family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: Execution unit General Purpose Register (GPR) Multiply/Divide Unit (MDU) System control coprocessor (CP0) Memory Management Unit (MMU) Instruction/Data cache controllers Power Management Instructions and data caches microMIPS support Enhanced JTAG (EJTAG) controller The processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. Seven additional register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: 32-bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results The processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32×32 booth recoded multiplier, four pairs of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32×32) represents the rs operand. The second number (‘32’ of 32×32) represents the rtoperand.
- Core: 200 MHz (up to 330 DMIPS) microAptiv™
- 16 KB I-Cache, 4 KB D-Cache
- MMU for optimum embedded OS execution
- microMIPS™ mode for up to 35% smaller code size
- DSP-enhanced core: – Four 64-bit accumulators – Single-cycle MAC, saturating and fractional math
- Code-efficient (C and Assembly) architecture Clock Management
- 0.9% internal oscillator
- Programmable PLLs and oscillator clock sources
- Fail-Safe Clock Monitor (FSCM)
- Independent Watchdog Timers (WDT) and Deadman Timer (DMT)
- Fast wake-up and start-up
- Power Management
- Low-power modes (Sleep and Idle)
- Integrated Power-on Reset and Brown-out Reset
- Memory Interfaces
- 50 MHz External Bus Interface (EBI)
- 50 MHz Serial Quad Interface (SQI) Audio and Graphics Interfaces
- Graphics interfaces: EBI or PMP
- Audio data communication: I2S, LJ, and RJ
- Audio control interfaces: SPI and I2 C™
- Audio master clock: Fractional clock frequencies with USB synchronization
- High-Speed (HS) Communication Interfaces (with Dedicated DMA)
- USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
- 10/100 Mbps Ethernet MAC with MII and RMII interface Security Features
- Crypto Engine with a RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC)
- Advanced memory protection: – Peripheral and memory region access control
- Direct Memory Access (DMA)
- Eight channels with automatic data size detection
- Programmable Cyclic Redundancy Check (CRC)
- Advanced Analog Features
- 10-bit ADC resolution and up to 48 analog inputs
- Flexible and independent ADC trigger sources
- Two comparators with 32 programmable voltage references
- Temperature sensor with ±2°C accuracy
- Communication Interfaces
- Two CAN modules (with dedicated DMA channels): – 2.0B Active with DeviceNet™ addressing support
- Six UART modules (25 Mbps): – Supports LIN 1.2 and IrDA® protocols
- Six 4-wire SPI modules
- SQI configurable as an additional SPI module (50 MHz)
- Five I2 C modules (up to 1 Mbaud) with SMBus support
- Parallel Master Port (PMP)
- Peripheral Pin Select (PPS) to enable function remap
- Timers/Output Compare/Input Capture
- Nine 16-bit or up to four 32-bit timers/counters
- Nine Output Compare (OC) modules
- Nine Input Capture (IC) modules
- PPS to enable function remap
- Real-Time Clock and Calendar (RTCC) module Input/Output
- 5V-tolerant pins with up to 32 mA source/sink
- Selectable open drain, pull-ups, and pull-downs
- External interrupts on all I/O pins
- Qualification and Class B Support
- AEC-Q100 REVG (Grade 2 -40°C to +105°C) Planned
- AEC-Q100 REVG (Grade 1 -40°C to +125°C) Planned
- Class B Safety Library, IEC 60730
- Back-up internal oscillator
- Debugger Development Support
- In-circuit and in-application programming
- 4-wire MIPS® Enhanced JTAG interface
- Unlimited software and 12 complex breakpoints
- IEEE 1149.2-compatible (JTAG) boundary scan
- Non-intrusive hardware-based instruction trace
- Software and Tools Support
- C/C++ compiler with native DSP/fractional support
- MPLAB® Harmony Integrated Software Framework
- TCP/IP, USB, Graphics, and mTouch™ middleware
- MFi, Android™, and Bluetooth® audio frameworks
- FreeRTOS™, OPENRTOS® , µC/OS™, and other popular RTOS kernels
