Description
This LSI is a microprocessor that integrates a 32-bit RISC-type SuperH architecture CPU as its core, together with 32-kbyte cache memory as well as peripheral functions required for system configuration such as an interrupt controller.High-speed data transfers can be formed by an on-chip direct memory access controller (DMAC), and an external memory access support function enables direct connection to different kinds of memory. This LSI also includes powerful peripheral functions that are essential to system configuration, such as USB (Function) functionality and a serial interface with a large FIFO.A powerful built-in power-management function keeps power consumption low, even during high-speed operation. This LSI is ideal for use in electronic devices such as those for applications that require both high speeds and low power consumption.
- Original Renesas SuperH architecture
- Compatible with SH-1, SH-2 and SH-3 at object code level
- 32-bit internal data bus
- General-registers
- Sixteen 32-bit general registers (eight 32-bit shadow registers)
- Five 32-bit control registers
- Four 32-bit system registers
- RISC-type instruction set
- Instruction length: 16-bit fixed length and improved code efficiency
- Load/store architecture
- Delayed branch instructions
- Instruction set based on C language
- Instruction execution time: one instruction/cycle for basic instructions
- Logical address space: 4 Gbytes
- Five-stage pipeline
