Description
The SH7065 is a CMOS single-chip microcomputer featuring an SH2-DSP core-a functionally enhanced version of the SuperH RISC engine using an original Renesas Technology architecture with the same signal processing capability as a general-purpose digital signal processor (DSP), together with peripheral functions required for system configuration.The SH2-DSP core offers enhancement of the DSP functions (multiply and multiply-and accumulate) of the SuperH RISC engine, and provides full DSP type data bus functionality, enabling efficient execution of various kinds of signal processing and image processing. With this CPU, it has become possible to create low-cost, high-performance/high-functionality systems even for applications such as real time control, which could not previously be handled by microcomputers because of their high-speed processing requirements.In addition, the SH7065 includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), A/D converter, D/A converter, interrupt controller (INTC), and I/O ports. An external memory access support function allows efficient connection of memory and peripheral LSIs, greatly reducing system cost.There are two versions of the SH7065, with different kinds of on-chip ROM: an F-ZTAT version with on-chip flash memory, and a mask ROM version. In the F-ZTAT version, programs can be written and rewritten with a Renesas-recommended ROM programmer, or on-board.
- Original Renesas Technology architecture
- 32-bit internal configuration
- General register machine
- Sixteen 32-bit general registers
- Six 32-bit control registers (including three added for DSP use)
- Ten 32-bit system registers (including six added for DSP use)
- RISC (reduced instruction set computer) type instruction set
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture (basic operations are executed between registers)
- Delayed branch instructions reduce pipeline disruption during branches
- C-oriented instruction set
- Instruction execution time: One instruction per cycle
- Address space: Architecture supports 4 Gbytes
- Enhanced on-chip multiplier:
- 16 × 16 ? 32 multiply operations executed in one to three cycles
- 32 × 32 ? 64 multiply operations executed in two to four cycles
- 32 × 32 + 64 ? 64 multiply-and-accumulate operations executed in two to four cycles
- Five-stage pipeline
