Description
The V850ES/SG3 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. The V850ES/SG3 includes an IEBus (Inter Equipment Bus) controller for the automotive LAN, and some of the models also include a CAN (Controller Area Network) controller.In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/SG3 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the V850ES/SG3 enables an extremely high cost-performance for applications that require a low power consumption, such as audio and car audio.
- Minimum instruction execution time: 31.25 ns (operating with main clock (fXX) of 32 MHz)
- General-purpose registers: 32 bits × 32 registers
- CPU features: Signed multiplication (16 × 16 ? 32): 1 to 2 clocks Signed multiplication (32 × 32 ? 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format
- Memory space: 64 MB of linear address space (for programs and data)
- External expansion: Up to 4 MB
- Internal memory: RAM: 24/32/40/48/60 KB
- Flash memory: 256/384/512/640/768/1024 KB
- External bus interface: Separate bus/multiplexed bus output selectable
- 8/16 bit data bus sizing function
- Wait function
- Programmable wait function
- External wait function
- Idle state function
- Bus hold function
- Interrupts and exceptions: Non-maskable interrupts: 2 sources
- Maskable interrupts: 59 sources
- Software exceptions: 32 sources
- Exception trap: 2 sources
- I/O lines: I/O ports: 84
- Timer function: 16-bit interval timer M (TMM): 1 channel
- 16-bit timer/event counter P (TMP): 6 channels
- 16-bit timer/event counter Q (TMQ): 1 channel
- Watch timer: 1 channel
- Watchdog timer: 1 channel
- Real-time output port: 6 bits × 1 channel
- Serial interface: Asynchronous serial interface A (UARTA)
- 3-wire variable-length serial interface B (CSIB)
- I2C bus interface (I2C)
- UARTA/CSIB: 1 channel
- UARTA/I2C: 2 channels
- CSIB/I2C: 1 channel
- CSIB: 3 channels
- IEBus controller: 1 channel
- CAN controller: 1 channel (CAN controller versions only)
- A/D converter: 10-bit resolution: 12 channels
- D/A converter: 8-bit resolution: 2 channels
- DMA controller: 4 channels
- CRC function: 16-bit error detection codes are generated for data in 8-bit units
- Debug control unit (DCU): JTAG interface
- ROM correction: 4 correction addresses specifiable
- Clock generator: During main clock or sub clock operation
- 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
- Clock-through mode/PLL mode selectable
- Internal oscillation clock: 220 kHz (TYP.)
- Power-save functions: HALT/IDLE1/IDLE2/STOP/sub clock/sub-IDLE mode
- Package: 100-pin plastic LQFP (fine pitch) (14 × 14)
