Description
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU. This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit free running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI), an I2C bus interface (IIC), an LPC interface (LPC), a D/A converter, an A/D converter, and I/O ports as on-chip peripheral modules required for system configuration. A data transfer controller (DTC) is included as a bus master.
- Upward-compatibility with H8/300 and H8/300H CPUs
- Can execute H8/300 CPU and H8/300H CPU object programs
- General-register architecture
- Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
- Sixty-five basic instructions
- 8/16/32-bit arithmetic and logic instructions
- Multiply and divide instructions
- Powerful bit-manipulation instructions
- Eight addressing modes
- Register direct [Rn]
- Register indirect [@ERn]
- Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
- Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
- Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
- Immediate [#xx:8, #xx:16, or #xx:32]
- Program-counter relative [@(d:8,PC) or @(d:16,PC)]
- Memory indirect [@@aa:8]
- 16 Mbytes address space
- Program: 16 Mbytes
- Data: 16 Mbytes
- High-speed operation
- All frequently-used instructions are executed in one or two states
- 8/16/32-bit register-register add/subtract: 1 state
- 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
- 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
- 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
- 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
