Description
Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz.
Ultra-Low Power Technology 1.6 V to 3.6 V operation from a single supply Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA Halt (RTC + LVD): 0.57 µA Snooze: 0.7 mA (UART), 0.6 mA (ADC) Operating: 66 µA/MHz 16-bit RL78 CPU Core Delivers 41 DMIPS at maximum operating frequency of 32 MHz Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles CISC Architecture (Harvard) with 3-stage pipeline Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle MAC: 16 x 16 to 32-bit result in 2 clock cycles 16-bit barrel shifter for shift & rotate in 1 clock cycle 1-wire on-chip debug function Code Flash Memory Density: 16 KB to 64 KB Block size: 1 KB On-chip single voltage flash memory with protection from block erase/writing Self-programming with secure boot swap function and flash shield window function
