Описание
The MC9S12NE64 is a 112-/80-pin cost-effective, low-end connectivity applications MCU family. The MC9S12NE64 is composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of FLASH EEPROM, 8K bytes of RAM, Ethernet media access controller (EMAC) with integrated 10/100 Mbps Ethernet physical transceiver (EPHY), two asynchronous serial communications interface modules (SCI), a serial peripheral interface (SPI), one inter-IC bus (IIC), a 4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ATD), up to 21 pins available as keypad wakeup inputs (KWU), and two additional external asynchronous interrupts. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. Furthermore, an on-chip bandgap-based voltage regulator (VREG_PHY) generates the internal digital supply voltage of 2.5 V (VDD) from a 3.15 V to 3.45 V external supply range. The MC9S12NE64 has full 16-bit data paths throughout. The 112-pin package version has a total of 70 I/O port pins and 10 input-only pins available. The 80-pin package version has a total of 38 I/O port pins and 10 input-only pins available. For rapid application development, the MC9S12NE64 demonstration board includes CodeWarrior Development Studio for HCS12(X) Microcontrollers, Special Edition. The Special Edition allows the designer to develop, compile, link and debug applications up to 32K in size. Processor Expert, which is integrated in the CodeWarrior tools, provides fully debugged peripheral drivers, libraries and interfaces that allow the programmer to create unique C application code.
- HCS12 CPU
- Upward compatible with M68HC11 instruction set
- Interrupt stacking and programmer’s model identical to M68HC11
- Instruction queue
- Enhanced indexed addressing
- Memory map and interface (MMC)
- Interrupt control (INT)
- Background debug mode (BDM)
- Enhanced debug12 module, including breakpoints and change-of-flow trace buffer (DBG)
- Multiplexed expansion bus interface (MEBI) — available only in 112-pin package version
- Up to 21 port bits available for wakeup interrupt function with digital filtering
- 64K bytes of FLASH EEPROM
- 8K bytes of RAM
- Two asynchronous serial communications interface (SCI)
- One synchronous serial peripheral interface (SPI)
- One inter-IC bus (IIC)
- IEEE 802.3 compliant
- Medium-independent interface (MII)
- Full-duplex and half-duplex modes
- Flow control using pause frames
- MII management function
- Address recognition
- Frames with broadcast address are always accepted or always rejected
- Exact match for single 48-bit individual (unicast) address
- Hash (64-bit hash) check of group (multicast) addresses
- Promiscuous mode
