Описание
The MC68HC908LD64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. With special modules such as the sync processor, on-screen display module, analog-to-digital converter, pulse modulator module, DDC12AB interface, multi-master IIC interface, and universal serial bus interface, the MC68HC908LD64 is designed specifically for use in digital monitor systems.
- High-performance M68HC08 architecture
- Fully upward-compatible object code with M6805, M146805, and M68HC05 families
- Low-power design; fully static with stop and wait modes
- 3.3V operating voltage
- 6MHz internal bus frequency; with 24MHz external crystal
- 60,928 bytes of on-chip FLASH memory with security1 feature
- 2,048 bytes of on-chip random access memory (RAM)
- 39 general-purpose input/output (I/O) pins, including:
- 38 shared-function I/O pins
- 8-bit keyboard interrupt port
- 2-channel, 16-bit timer interface module (TIM) with selectable input capture, output compare, and PWM capability on one channel
- 6-channel, 8-bit analog-to-digital converter (ADC)
- 8-channel, 8-bit pulse width modulator (PWM)
- Sync signal processor with the following features:
- Horizontal and vertical frequency counters
- Low vertical frequency indicator (40.7Hz)
- Polarity controlled Hsync and Vsync outputs from separate sync or composite sync inputs
- Internal generated free-running Hsync, Vsync, DE, and DCLK
- CLAMP pulse output to the external pre-amp chip
- On screen display (OSD) and full screen pattern display
- Full Universal Serial Bus (USB) specification 1.1, composite hub with embedded functions, including:
- One 12MHz upstream port
- Four 12MHz/1.5MHz downstream ports
- One hub control endpoint with 8-byte transmit buffer and 8-byte receive buffer
- One hub interrupt endpoint with 1-byte transmit buffer
- One device control endpoint with 8-byte transmit buffer and 8-byte receive buffer
- Two device interrupt endpoints with shared 8-byte transmit buffer
- DDC12AB1 module with the following:
- DDC1 hardware
- Multi-master IIC2 hardware for DDC2AB; with dual address
- Additional multi-master IIC module
- In-system programming capability using USB or DDC12AB communication, or standard serial link on PTA0 pin
- System protection features:
- Optional computer operating properly (COP) reset
- Illegal opcode detection with reset
- Illegal address detection with reset
- Master reset pin (with internal pull-up) and power-on reset
- IRQ interrupt pin with internal pull-up and schmitt-trigger input
- 64-pin quad flat pack (QFP) package
