MCU 8-bit H8 CISC 16KB Flash 3.3V/5V 80-Pin TQFP, HD64F3642AWV, Renesas Electronics

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation.

  • Features of the H8/300L CPU are listed below.
  • General-register architecture
    • Sixteen 8-bit general registers, also usable as eight 16-bit general registers
  • Instruction set with 55 basic instructions, including:
    • Multiply and divide instructions
    • Powerful bit-manipulation instructions
  • Eight addressing modes
    • Register direct
    • Register indirect
    • Register indirect with displacement
    • Register indirect with post-increment or pre-decrement
    • Absolute address
    • Immediate
    • Program-counter relative
    • Memory indirect
  • 64-kbyte address space
  • High-speed operation
    • All frequently used instructions are executed in two to four states
    • High-speed arithmetic and logic operations
  • Low-power operation modes
    • SLEEP instruction for transfer to low-power operation

Характеристики

Бренд

Operating_supply_voltage

3.3, 5 V

Min_operating_supply_voltage

2.7 V

Max_operating_supply_voltage

5.5 V

Watchdog

1

Supplier_package

TQFP

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/RNSA/RNSAS06977/RNSAS06977-1.pdf?hkey=52A5661711E402568146F3353EA87419

Schedule_b

8542310000

Ram_size

1 KB

Program_memory_type

Flash

Program_memory_size

16 KB

Product_dimensions

12 x 12 x 1 mm

Pin_count

80

Operating_temperature

-20 to 75 °C

On_chip_adc

8-chx8-bit

Country_of_origin

United States

Number_of_timers

4

Number_of_programmable_i_os

45

Msl_level

3

Mounting

Surface Mount

Maximum_speed

8 MHz

Max_processing_temp

260

Lead_finish

Tin/Bismuth

Тип интерфейса

SCI

Instruction_set_architecture

CISC

Htsn

8542310001

Eccn

EAR99

Data_bus_width

8 Bit

Max_expanded_memory_size

64 KB

SKU: HD64F3642AWV

Description

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation.

  • Features of the H8/300L CPU are listed below.
  • General-register architecture
    • Sixteen 8-bit general registers, also usable as eight 16-bit general registers
  • Instruction set with 55 basic instructions, including:
    • Multiply and divide instructions
    • Powerful bit-manipulation instructions
  • Eight addressing modes
    • Register direct
    • Register indirect
    • Register indirect with displacement
    • Register indirect with post-increment or pre-decrement
    • Absolute address
    • Immediate
    • Program-counter relative
    • Memory indirect
  • 64-kbyte address space
  • High-speed operation
    • All frequently used instructions are executed in two to four states
    • High-speed arithmetic and logic operations
  • Low-power operation modes
    • SLEEP instruction for transfer to low-power operation

Additional information

Бренд

Operating_supply_voltage

3.3, 5 V

Min_operating_supply_voltage

2.7 V

Max_operating_supply_voltage

5.5 V

Watchdog

1

Supplier_package

TQFP

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/RNSA/RNSAS06977/RNSAS06977-1.pdf?hkey=52A5661711E402568146F3353EA87419

Schedule_b

8542310000

Ram_size

1 KB

Program_memory_type

Flash

Program_memory_size

16 KB

Product_dimensions

12 x 12 x 1 mm

Pin_count

80

Operating_temperature

-20 to 75 °C

On_chip_adc

8-chx8-bit

Country_of_origin

United States

Number_of_timers

4

Number_of_programmable_i_os

45

Msl_level

3

Mounting

Surface Mount

Maximum_speed

8 MHz

Max_processing_temp

260

Lead_finish

Tin/Bismuth

Тип интерфейса

SCI

Instruction_set_architecture

CISC

Htsn

8542310001

Eccn

EAR99

Data_bus_width

8 Bit

Max_expanded_memory_size

64 KB