MCU 8-bit AT89 8051 CISC 32KB Flash 3.3V/5V 44-Pin TQFP Tray, AT89LP51RC2-20AU, Microchip

The AT89LP51RC2 is a low-power, high-performance CMOS 8-bit 8051 microcontroller with 24/32 KB of In-System Programmable Flash program memory. The devices are manufactured using high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set. The AT89LP51RC2 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP51RC2, standard instructions need only one to four clock cycles providing six to twelve times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reducing power consumption and EMI. The AT89LP51RC2 also includes a compatibility mode that will enable classic 12 clock per machine cycle operation for true timing compatibility with the AT89LP51RC2. The AT89LP51RC2 retains all of the standard features of the AT89LP51RC2, including: 24KB/32KB of In-System Programmable Flash program memory, 256 bytes of RAM, 1152 bytes of expanded RAM, up to 40 I/O lines, three 16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four level, ten-vector interrupt system. The AT89LP51RC2 includes an On-Chip Debug (OCD) interface that allows read-modify-write capabilities of the system state and program flow control, and programming of the internal memories. The on-chip Flash may also be programmed through the UART-based boot loader or the SPI-based In-System programming interface (ISP).

  • 8-bit Microcontroller Compatible with 8051 Products
  • Enhanced 8051 Architecture
    • Single Clock Cycle per Byte Fetch
    • 12 Clock per Machine Cycle Compatibility Mode
    • Up to 20 MIPS Throughput at 20 MHz Clock Frequency
    • Fully Static Operation: 0 Hz to 20 MHz
    • On-chip 2-cycle Hardware Multiplier
    • 16×16 Multiply Accumulate Unit
    • 256 x 8 Internal RAM
    • On-chip 1152 Bytes Expanded RAM (ERAM)
  • Software Selectable Size (0, 256, 512, 768, 1024 or 1152 Bytes)
    • Dual Data Pointers
    • 4-level Interrupt Priority
  • Nonvolatile Program and Data Memory
    • 32KB of In-System Programmable (ISP) Flash Program Memory
    • 512-byte User Signature Array
    • Endurance: 10,000 Write/Erase Cycles
    • Serial Interface for Program Downloading
    • 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Boot loader
  • Peripheral Features
    • Three 16-bit Enhanced Timer/Counters
    • Seven 8-bit PWM Outputs
    • 16-bit Programmable Counter Array
  • High Speed Output, Compare/Capture
  • Pulse Width Modulation, Watchdog Timer Capabilities
    • Enhanced UART with Automatic Address Recognition and Framing Error Detection
    • Enhanced Master/Slave SPI with Double-buffered Send/Receive
    • Two Wire Interface 400K bit/s
    • Programmable Watchdog Timer with Software Reset
    • 8 General-purpose Interrupt and Keyboard Interface Pins
  • Special Microcontroller Features
    • Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51IC2)
    • Two-wire On-Chip Debug Interface
    • Brown-out Detection and Power-on Reset with Power-off Flag
    • Selectable Polarity External Reset Pin
    • Low Power Idle and Power-down Modes
    • Interrupt Recovery from Power-down Mode
    • 8-bit Clock Prescaler
  • I/O and Packages
    • Up to 40 Programmable I/O Lines
    • Green (Pb/Halide-free) PLCC44, VQFP44, QFN44. PDIP40
    • Configurable I/O Modes
  • Quasi-bidirectional (80C51 Style), Input-only (Tristate)
  • Push-pull CMOS Output, Open-drain
  • Operating Conditions
    • 2.4V to 5.5V VCC Voltage Range
    • -40°C to 85°C Temperature Range
    • 0 to 20 MHz @ 2.4V – 5.5V (Single-cycle)

Характеристики

Analog_comparators

2

Operating_temperature

-40 to 85 °C

Max_operating_supply_voltage

5.5 V

Watchdog

1

Supplier_package

TQFP

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/ATML/ATMLS06156/ATMLS06156-1.pdf?hkey=52A5661711E402568146F3353EA87419

Screening_level

Industrial

Schedule_b

8542310000

Ram_size

256 KB

Program_memory_type

Flash

Program_memory_size

32 Kb

Product_dimensions

10.1 x 10.1 x 1.05 mm

Pin_count

44

Operating_supply_voltage

3.3, 5 V

Бренд

On_chip_adc

8-chx10-bit

Number_of_timers

3

Number_of_programmable_i_os

40

Mounting

Surface Mount

Maximum_speed

20 MHz

Тип интерфейса

SPI/UART

Instruction_set_architecture

CISC

Htsn

8542310001

Eccn

EAR99

Device_core

8051

Data_bus_width

8 Bit

Country_of_origin

China

Min_operating_supply_voltage

2.4 V

Артикул: AT89LP51RC2-20AU

Описание

The AT89LP51RC2 is a low-power, high-performance CMOS 8-bit 8051 microcontroller with 24/32 KB of In-System Programmable Flash program memory. The devices are manufactured using high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set. The AT89LP51RC2 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP51RC2, standard instructions need only one to four clock cycles providing six to twelve times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reducing power consumption and EMI. The AT89LP51RC2 also includes a compatibility mode that will enable classic 12 clock per machine cycle operation for true timing compatibility with the AT89LP51RC2. The AT89LP51RC2 retains all of the standard features of the AT89LP51RC2, including: 24KB/32KB of In-System Programmable Flash program memory, 256 bytes of RAM, 1152 bytes of expanded RAM, up to 40 I/O lines, three 16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four level, ten-vector interrupt system. The AT89LP51RC2 includes an On-Chip Debug (OCD) interface that allows read-modify-write capabilities of the system state and program flow control, and programming of the internal memories. The on-chip Flash may also be programmed through the UART-based boot loader or the SPI-based In-System programming interface (ISP).

  • 8-bit Microcontroller Compatible with 8051 Products
  • Enhanced 8051 Architecture
    • Single Clock Cycle per Byte Fetch
    • 12 Clock per Machine Cycle Compatibility Mode
    • Up to 20 MIPS Throughput at 20 MHz Clock Frequency
    • Fully Static Operation: 0 Hz to 20 MHz
    • On-chip 2-cycle Hardware Multiplier
    • 16×16 Multiply Accumulate Unit
    • 256 x 8 Internal RAM
    • On-chip 1152 Bytes Expanded RAM (ERAM)
  • Software Selectable Size (0, 256, 512, 768, 1024 or 1152 Bytes)
    • Dual Data Pointers
    • 4-level Interrupt Priority
  • Nonvolatile Program and Data Memory
    • 32KB of In-System Programmable (ISP) Flash Program Memory
    • 512-byte User Signature Array
    • Endurance: 10,000 Write/Erase Cycles
    • Serial Interface for Program Downloading
    • 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Boot loader
  • Peripheral Features
    • Three 16-bit Enhanced Timer/Counters
    • Seven 8-bit PWM Outputs
    • 16-bit Programmable Counter Array
  • High Speed Output, Compare/Capture
  • Pulse Width Modulation, Watchdog Timer Capabilities
    • Enhanced UART with Automatic Address Recognition and Framing Error Detection
    • Enhanced Master/Slave SPI with Double-buffered Send/Receive
    • Two Wire Interface 400K bit/s
    • Programmable Watchdog Timer with Software Reset
    • 8 General-purpose Interrupt and Keyboard Interface Pins
  • Special Microcontroller Features
    • Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51IC2)
    • Two-wire On-Chip Debug Interface
    • Brown-out Detection and Power-on Reset with Power-off Flag
    • Selectable Polarity External Reset Pin
    • Low Power Idle and Power-down Modes
    • Interrupt Recovery from Power-down Mode
    • 8-bit Clock Prescaler
  • I/O and Packages
    • Up to 40 Programmable I/O Lines
    • Green (Pb/Halide-free) PLCC44, VQFP44, QFN44. PDIP40
    • Configurable I/O Modes
  • Quasi-bidirectional (80C51 Style), Input-only (Tristate)
  • Push-pull CMOS Output, Open-drain
  • Operating Conditions
    • 2.4V to 5.5V VCC Voltage Range
    • -40°C to 85°C Temperature Range
    • 0 to 20 MHz @ 2.4V – 5.5V (Single-cycle)

Детали

Analog_comparators

2

Operating_temperature

-40 to 85 °C

Max_operating_supply_voltage

5.5 V

Watchdog

1

Supplier_package

TQFP

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/ATML/ATMLS06156/ATMLS06156-1.pdf?hkey=52A5661711E402568146F3353EA87419

Screening_level

Industrial

Schedule_b

8542310000

Ram_size

256 KB

Program_memory_type

Flash

Program_memory_size

32 Kb

Product_dimensions

10.1 x 10.1 x 1.05 mm

Pin_count

44

Operating_supply_voltage

3.3, 5 V

Бренд

On_chip_adc

8-chx10-bit

Number_of_timers

3

Number_of_programmable_i_os

40

Mounting

Surface Mount

Maximum_speed

20 MHz

Тип интерфейса

SPI/UART

Instruction_set_architecture

CISC

Htsn

8542310001

Eccn

EAR99

Device_core

8051

Data_bus_width

8 Bit

Country_of_origin

China

Min_operating_supply_voltage

2.4 V