Description
The H8/3337 Series and the H8/3397 Series of single-chip microcomputers feature an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions.The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, four types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog timer), a serial communication interface (SCI), an I2 C bus interface (option), a host interface (HIF), an A/D converter, a D/A converter, and I/O ports. The H8/3397 Series is a subset of the H8/3337 Series and does not include an I2 C bus interface, host interface, and D/A converter.
- CPU
- Two-way general register configuration
- Eight 16-bit registers, or
- Sixteen 8-bit registers
- Maximum clock rate (ø clock): 16 MHz at 5 V, 12MHz at 4 V or 10 MHz at 3 V
- 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12MHz), 200 ns (10 MHz)
- 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz)
- 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz)
- Instruction length: 2 or 4 bytes
- Register-register arithmetic and logic operations
- MOV instruction for data transfer between registers and memory
- Multiply instruction (8 bits × 8 bits)
- Divide instruction (16 bits ÷ 8 bits)
- Bit-accumulator instructions
- Register-indirect specification of bit positions
- 16-bit free-running timer (1 channel)
- One 16-bit free-running counter (can also count external events)
- Two output-compare lines
- Four input capture lines (can be buffered)
- 8-bit timer (2 channels)
- Each channel has
- One 8-bit up-counter (can also count external events)
- Two time constant registers
- PWM timer (2 channels)
- Duty cycle can be set from 0 to 100%
- Resolution: 1/250
- Watchdog timer (WDT) (1 channel)
- Overflow can generate a reset or NMI interrupt
- Also usable as interval timer
- Serial communication interface (SCI) (2 channels)
- Asynchronous or synchronous mode (selectable)
- Full duplex: can transmit and receive simultaneously
- On-chip baud rate generator
- Host interface (HIF)
- 8-bit host interface port
- Three host interrupt requests (HIRQ1, HIRQ11, HIRQ12)
- Regular and fast A20 gate output
- Two register sets, each with two data registers and a status register
- I/O ports
- 74 input/output lines (16 of which can drive LEDs)
- 8 input-only lines
- Interrupts
- Nine external interrupt lines: NMI, IRQ0 to IRQ7
- 26 on-chip interrupt sources
- Operating modes
- Expanded mode with on-chip ROM disabled (mode 1)
- Expanded mode with on-chip ROM disabled (mode 1)
- Single-chip mode (mode 3)
- Power-down modes
- Sleep mode
- Software standby mode
- Hardware standby mode
- Other features
- On-chip clock pulse generator
